As known in the art, a color liquid crystal display (LCD) panel 1 has a two-dimensional array of pixels 10, as shown in FIG. 1. The array of pixels 10 is organized in rows and columns and a plurality of gate lines are used to select or activate the pixels in the rows and a plurality of data lines are used to provide data to the pixels in the columns. Thus, the LCD panel 1 generally has a gate driver 300 to provide gate-line signals in the gate-lines and a data driver 200 to provide data signals to the data lines.
The gate driver 300 generally includes a plurality of shift registers connected in a cascade fashion, such that the output signal from a shift register is used as a gate-line signal to a gate line and also as a start pulse to the shift register in the next stage. As shown in FIG. 2, while the start pulse for the first stage shift register SR1 is separately provided by a ST signal, the start pulse for each of the shift registers in the following stages is provided by the shift register in the immediately preceding stage. As shown in FIG. 2, the clock input CK of the odd-numbered shift registers receives a clock signal CK and the clock input CK of the even-numbered shift registers receives a clock signal from XCK. As shown in FIG. 3, the clock signal XCK is complementary of the clock signal CK, which has a 50% duty cycle.
In a gate driver fabricated using a gate-on-array (GOA) technology, the voltage levels (Vgh=23V and Vgl=−10V) for the clock signals are boosted from a low voltage waveform by a voltage level shifter. While the shift registers are fabricated on a glass substrate, the voltage level shifter IC is implemented on a printed wire board (PWB) or printed circuit board (PCB). A flexible printed circuit (FPC) is generally used to provide connections between the glass substrate and the PWB or PCB. Because of the high peak-to-peak voltage difference in the clock signals and the large number of the shift registers connected to the clock signals, the power consumption by the parasitic capacitance is high and wasteful.
One way to reduce the power consumption by the parasitic capacitance is to use a charge sharing scheme for reducing the sudden increase or the sudden drop from one voltage level to another voltage level in the clock signals. As shown in FIG. 4a, a voltage level shifter having an input end to receive a clock signal CK_in and its complementary clock signal XCK_in (see FIG. 4b) and a control voltage VCS of about 3.3V. The voltage level shifter also has two voltage amplifiers A1 and A2 to provide the output clock signals CK and XCK. Schematically, a switch S1 is provided between the amplifier A1 and the output CK and a switch S2 is provided between the amplifier A2 and the output XCK. A third switch S3 and a resistor R are connected in series between CK and XCK. The timing for operating the switches S1, S2 and S3 is as follows:
In time periods 1, 3 and 4, S1 and S2 are closed or in the connecting state and S3 is open or in disconnecting state. Thus, the voltage levels at CK and XCK are those at the output of A1 and the output of A2, respectively.
In time periods 2 and 4, both S1 and S2 are in the disconnecting state while S3 is in the connecting state for charge-sharing between CK and XCK.
While the power consumption due to such a charge-sharing scheme can be reduced, a delay in turning on a gate line may occur.